Publikációk

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Szűrők: Szerző = András Pataricza  [Minden szűrő visszaállítása]
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Varró, D., and Pataricza, A., An XML Schema Description of Graph Transformation Systems, : Budapest University of Technology and Economics, Department of Measurement and Information Systems, January, 2001. Abstract
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Varró, D., and Pataricza, A., "VPM: A visual, precise and multilevel metamodeling framework for describing mathematical domains and UML", Journal of Software and Systems Modeling, vol. 2, no. 3: Springer, pp. 187–210, October, 2003. Abstract
Csertán, G., Huszerl, G., Majzik, I., Pap, Z., Pataricza, A., and Varró, D., "VIATRA: Visual Automated Transformations for Formal Verification and Validation of UML Models", Proc. ASE 2002: 17th IEEE International Conference on Automated Software Engineering, Edinburgh, UK, IEEE Press, pp. 267–270, September 23–27, 2002. Abstract

Acceptance rate = 20%

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Varró, D., Domokos, P., and Pataricza, A., UML Specification of Model Transformation Systems, : Budapest University of Technology and Economics, Department of Measurement and Information Systems, October, 2000. Abstract
Varró, D., and Pataricza, A., "UML modellek automatikus transzformációi", OOOK 2002: 5. Országos Objektum-Orientált Konferencia, Dobogókõ, Hungary, October 16–17, 2002.

In Hungarian

Varró, D., and Pataricza, A., "UML Action Semantics for Model Transformation Systems", Periodica Polytechnica, vol. 47, no. 3, pp. 167–186, 2003. Abstract
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Pataricza, A., Varró, D., Majzik, I., Polgár, B., Ráth, I., and Horváth, Á., "Workflow-Driven Tool Integration Using Model Transformation", Graph Transformations and Model Driven Enginering - Essays Dedicated to Manfred Nagl on the Occasion of his 65th Birthday: Springer, pp. 224-248, 2010.
Pataricza, A., Majzik, I., Hohl, W., and Hönig, J., "Watchdog Processors in Parallel Systems", MICROPROCESSING AND MICROPROGRAMMING, vol. 39, issue 2-5, pp. 69 - 74, 1993. Abstract
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Varró, D., Varró, G., and Pataricza, A., "Visual Graph Transformation in System Verification", DDECS 2000 International IEEE Workshop on the Design and Diagnostics of Electronic Circuits and Systems, Bratislava, Slovakia, pp. 137–141, April 5–7, 2000. Abstract
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Varró, D., and Pataricza, A., A Unifying Semantic Framework for Multilevel Metamodelling, : Budapest University of Technology and Economics, October, 2001.
Pataricza, A., Majzik, I., Huszerl, G., and Várnai, G., "UML-based Design and Formal Analysis of a Safety-Critical Railway Control Software Module", Formal Methods for Railway Operation and Control Systems, Budapest, L'Harmattan Kiadó, pp. 125 - 132, 2003.
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Darabos, A., Pataricza, A., and Varró, D., "Towards Testing the Implementation of Graph Transformations", Proc. of the Fifth International Workshop on Graph Transformation and Visual Modelling Techniques: Elsevier, 2006. Abstract
Varró, D., Varró, G., and Pataricza, A., Towards an XMI–Based Model Interchange Format for Graph Transformation Systems, : Budapest University of Technology and Economics, Department of Measurement and Information Systems, September, 2000. Abstract
Majzik, I., and Pataricza, A., "Többprocesszoros rendszerek ellenőrzése watchdog processzorok felhasználásával", XIV. Tudományos Ülésszak, Kandó Kálmán Műszaki Főiskola, pp. - , 1994.
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Paljak, G J., Kocsis, I., Égel, Z., Tóth, D., and Pataricza, A., "Sensor Selection for IT Infrastructure Monitoring", Autonomic Computing and Communications Systems, vol. 23: Springer Berlin Heidelberg, pp. 130-143, 2010.

10.1007/978-3-642-11482-3_9

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Csertán, G., Majzik, I., Pataricza, A., and Allmaier, S., "Reachability Analysis of Petri-nets by FPGA Based Accelerators", Proc. Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS'98), pp. 307 - 312, 1998.
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Paljak, G J., Égel, Z., Tóth, D., Kocsis, I., Kovácsházy, T., and Pataricza, A., "Qualitative performance control in supervised IT infrastructures", Dependable Systems and Networks Workshops (DSN-W), 2010 International Conference on, pp. 59 -65, jun., 2010.
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Polgár, B., Nováki, S., Pataricza, A., and Friedler, F., "A Process Graph Based Formulation of The Syndrome-decoding Problem", Proc. IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS 2001): SZIF-Universitas, pp. 267 - 272, 2001.
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Majzik, I., Hohl, W., Pataricza, A., and Sieh, V., "Multiprocessor Checking Using Watchdog Processors", COMPUTER SYSTEMS SCIENCE AND ENGINEERING, vol. 11, issue 5, pp. 301 - 310, 1996. Abstract
Tóth, A., Varró, D., and Pataricza, A., "Model-Level Automatic Test Generation for UML Statecharts", Proc. 6th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2003), Poznan, Poland, pp. 293–294, April 14–16, 2003.