Exploiting Hierarchy in the Abstraction-Based Verification of Statecharts Using SMT Solvers

TitleExploiting Hierarchy in the Abstraction-Based Verification of Statecharts Using SMT Solvers
Publication TypeBook Chapter
Year of Publication2017
AuthorsCzipó, B., Hajdu, Á., Tóth, T., and Majzik, I.
EditorKofroň, J., and Tumova, J.
Book TitleProceedings of the 14th International Workshop on Formal Engineering Approaches to Software Components and Architectures
Series TitleElectronic Proceedings in Theoretical Computer Science
PublisherOpen Publishing Association

Statecharts are frequently used as a modeling formalism in the design of state-based systems. Formal verification techniques are also often applied to prove certain properties about the behavior of the system. One of the most efficient techniques for formal verification is Counterexample-Guided Abstraction Refinement (CEGAR), which reduces the complexity of systems by automatically building and refining abstractions. In our paper we present a novel adaptation of the CEGAR approach to hierarchical statechart models. First we introduce an encoding of the statechart to logical formulas that preserves information about the state hierarchy. Based on this encoding we propose abstraction and refinement techniques that utilize the hierarchical structure of statecharts and also handle variables in the model. The encoding allows us to use SMT solvers for the systematic exploration and verification of the abstract model, including also bounded model checking. We demonstrate the applicability and efficiency of our abstraction techniques with measurements on an industry-motivated example.