András Pataricza

2000
Varró, D., Varró, G., and Pataricza, A., "Visual Graph Transformation in System Verification", DDECS 2000 International IEEE Workshop on the Design and Diagnostics of Electronic Circuits and Systems, Bratislava, Slovakia, pp. 137–141, April 5–7, 2000. Abstract
Pap, Z., Majzik, I., Pataricza, A., and Szegi, A., "Completeness and Consistency Analysis of UML Statechart Specifications", 11th European Workshop on Dependable Computing (EWDC-11), Budapest, pp. 6 - , 2000.
Varró, D., Varró, G., and Pataricza, A., Towards an XMI–Based Model Interchange Format for Graph Transformation Systems, : Budapest University of Technology and Economics, Department of Measurement and Information Systems, September, 2000. Abstract
Varró, D., Domokos, P., and Pataricza, A., UML Specification of Model Transformation Systems, : Budapest University of Technology and Economics, Department of Measurement and Information Systems, October, 2000. Abstract
Varró, D., and Pataricza, A., Mathematical Model Transformation for System Verification, : Budapest University of Technology and Economics, Dept. of Measurement and Information Systems, June, 2000. Abstract
1999
Majzik, I., Jávorszky, J., Pataricza, A., and Selényi, E., "Concurrent Error Detection of Program Execution Based on Statechart Specification", Proc. 10th European Workshop on Dependable Computing (EWDC-10): Österreichische Computer Gesellschaft, pp. 181 - 185, 1999.
1998
Csertán, G., Majzik, I., Pataricza, A., Allmaier, S., and Hohl, W., "Hardware Accelerators for Petri-net Analysis", Proc. Austrian-Hungarian Workshop on Distributed and Parallel Systems (DAPSYS'98): University of Vienna, Department of Applied Computer Science, pp. 99 - 104, 1998.
Csertán, G., Majzik, I., Pataricza, A., and Allmaier, S., "Reachability Analysis of Petri-nets by FPGA Based Accelerators", Proc. Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS'98), pp. 307 - 312, 1998.
1996
Majzik, I., Hohl, W., Pataricza, A., and Sieh, V., "Multiprocessor Checking Using Watchdog Processors", COMPUTER SYSTEMS SCIENCE AND ENGINEERING, vol. 11, issue 5, pp. 301 - 310, 1996. Abstract
1995
Majzik, I., and Pataricza, A., "Control Flow Checking in Multitasking Systems", PERIODICA POLYTECHNICA-ELECTRICAL ENGINEERING, vol. 39, issue 1, pp. 27 - 36, 1995.
1994
Majzik, I., Pataricza, A., Dal Cin, M., Hohl, W., Hönig, J., and Sieh, V., "Hierarchical Checking of Multiprocessors Using Watchdog Processors", Dependable Computing - EDCC-1, Berlin ; Heidelberg, Springer-Verlag, pp. 386 - 403, 1994.
Majzik, I., Pataricza, A., Hohl, W., Hönig, J., and Sieh, V., "A High-Speed Watchdog Processor for Multitasking Systems", Proc. Eighth Symposium on Microcomputer and Microprocessor Applications (uP'94): HTE, pp. 65 - 74, 1994.
Majzik, I., and Pataricza, A., "Többprocesszoros rendszerek ellenőrzése watchdog processzorok felhasználásával", XIV. Tudományos Ülésszak, Kandó Kálmán Műszaki Főiskola, pp. - , 1994.
1993
Pataricza, A., Majzik, I., Hohl, W., and Hönig, J., "Watchdog Processors in Parallel Systems", MICROPROCESSING AND MICROPROGRAMMING, vol. 39, issue 2-5, pp. 69 - 74, 1993. Abstract

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