Visual Graph Transformation in System Verification

TitleVisual Graph Transformation in System Verification
Publication TypeConference Paper
Year of Publication2000
AuthorsVarró, D., Varró, G., and Pataricza, A.
EditorGramatova, E., Manhaeve, H., and Pawlak, A.
Conference NameDDECS 2000 International IEEE Workshop on the Design and Diagnostics of Electronic Circuits and Systems
Date PublishedApril 5–7
Conference LocationBratislava, Slovakia
Keywordsdeductive databases, formal verification, graph transformation, planner algorithms, visual languages
AbstractThe use of formal verification methods is essential in the design process of dependable computer controlled systems. A complex environment should support the semi-formal specification as well as the formal verification of the desired system. The efficiency of applying these formal methods will be highly increased if the underlying mathematical background is hidden from the designer. In such an integrated system effective techniques are needed to transform the system model to different sort of mathematical models supporting the assessment of system characteristics. The current paper introduces our research results towards a general-purpose model transformation engine. This approach results in yielding a provenly correct and complete transformation code by combining the powerful techniques of graph transformation, planner algorithms and deductive databases.